CMOS Image sensors (CIS) suffer from the issue that deeply scaled sub-micron Complementary Metal Oxide Semiconductor (CMOS) processes are required to realize small pixels that can compete with charge-coupled device (CCD) pixel sizes. In general, as the CMOS processes scale to smaller dimensions, the details of the process integration and structure change, and the pixel performance degrades. Two examples of this are shallow trench isolation and heavily doped retrograde wells. Both are necessary to build deep sub-micron CMOS devices, but both have adverse effects on dark current for pixels. As a result, much work has to be done to re-integrate and re-optimize the photodetector and pixel into each new deep sub-micron CMOS technology node.
Designers, however, face a trade-off with respect to the design and manufacture of sub-micron CMOS devices. Designers can either maintain pixel image quality by not moving to more scaled CMOS processes, which results in a lower fill factor for smaller pixels, or move to a smaller design rule process to achieve small pixels, which results in a need to re-integrate and re-engineer the photodetector to obtain acceptable image quality.
One solution to these issues is to build the photodetector separately from the CMOS circuits. The image sensor, for example, can be built on different wafers, and the wafers joined together using three-dimensional integration or wafer level interconnect technologies. U.S. Pat. No. 6,927,432 fabricates an active pixel sensor using two semiconductor wafers. One wafer, the donor wafer, includes the photodetectors while another wafer, the host wafer, includes an interconnect layer and electrical circuits for in-pixel signal operations and read out of the photodetectors. Pixel interconnects directly connect each photodetector on the donor wafer to a respective node or circuit on the host wafer.
Although this approach separates the processing of the photodetector and circuits, it degrades photodetector performance due to the direct contact or connection with the photodetector. Specific examples of such performance degradation include, but are not limited to, increased dark current due to damage from the contact etch process, increased metallic contamination in the photodetector leading to point defects, and high dark current due to being connected to a highly doped ohmic contact region.
FIG. 1 is a schematic diagram of another pixel architecture that can be implemented on two semiconductor wafers in accordance with the prior art.
This pixel architecture is disclosed in commonly assigned U.S. patent application Ser. No. 11/867,199 filed on Oct. 4, 2007. Pixel 100 includes photodetector 102, transfer gate 104, charge-to-voltage conversion mechanism 106(SW), 106(CW), reset transistor 108, potential VDD 110, source follower amplifier transistor 112, and row select transistor 114. The drain of row select transistor 114 is connected to the source of source follower 112 and the source of row select transistor 114 is connected to output Vout 116. The drains of reset gate 108 and source follower 112 are maintained at potential VDD 110. The source of reset gate 108 and the gate of source follower 112 are connected to charge-to-voltage conversion mechanism 106(CW).
Dashed lines 118 surround photodetector 102, transfer gate 104, and charge-to-voltage conversion mechanism 106(SW) to delineate the components included on one wafer, a sensor wafer. Charge-to-voltage conversion mechanism 106(CW), reset gate transistor 108, potential VDD 110, source follower amplifier transistor 112, row select transistor 114, output 116, which are not surrounded by dashed lines 118, represent the components formed on a second wafer, a circuit wafer. Inter-wafer connection 120 electrically connects charge-to-voltage conversion mechanism 106(SW) on the sensor wafer to charge-to-voltage conversion mechanism 106(CW) on the circuit wafer.
Image sensors having pixels with the architecture shown in FIG. 1 require a charge-to-voltage conversion mechanism on each wafer. This requirement increases the cost to manufacture such image sensors because both the sensor wafer and the circuit wafer must be processed as cleanly as possible. Additionally, the use of inter-wafer connection 120 as a common node for charge-to-voltage conversion mechanism 106(SW), 106(CW), reset transistor 108, and source follower amplifier transistor 112 increases the capacitance in the connection.